FIG. 1 is a block diagram showing the configuration of a conventional OFDM (Orthogonal Frequency Division Multiplex) transmission apparatus 10 and OFDM reception apparatus 20. First, the configuration of OFDM transmission apparatus 10 will be explained. Transmission data of a bit sequence is subjected to channel coding (turbo coding) by coder 11, and the coded signal is subjected to data iteration processing and puncturing processing (rate matching processing) by rate matching section 12. The signal after the rate matching processing is subjected to data modulation mapping by modulation section 13 and output to IFFT (Inverse Fast Fourier Transform) section 14.
The signal output from modulation section 13 is subjected to an inverse fast Fourier transform by IFFT section 14, and an OFDM signal is thereby formed and a guard interval is inserted into the OFDM signal by GI (Guard Interval) insertion section 15. The OFDM signal with the guard interval inserted is converted from a digital signal to an analog signal by D/A conversion section 16, and the analog signal is up-converted to a radio frequency by RF (Radio Frequency) conversion section 17 and sent to OFDM reception apparatus 20 through antenna 18.
Next, the configuration of OFDM reception apparatus 20 will be explained. Noise is superimposed on the signal sent from OFDM transmission apparatus 10 over the propagation path and the signal is received by antenna 21. The signal received by antenna 21 is down-converted from a radio frequency to an intermediate frequency by RF conversion section 22, separated (subjected to quadrature detection) into signals of I component and Q component channels and then output to A/D conversion section 23. The signals of the I component and Q component channels are converted from analog to digital by A/D conversion section 23, and with guard intervals removed by GI removing section 24, the digital signals are output to FFT (Fast Fourier Transform) section 25.
The signals output from GI removing section 24 are separated into sequences in subcarrier units by FFT section 25 and the separated signals are demodulated by demodulation section 26. The demodulated signals are subjected to rate dematching processing by rate dematching section 27 and the signals subjected to the rate dematching processing are separated into three sequences by separation section 28. The same number of bits are deleted from the three separated sequences by bit number reduction section 29 and each sequence from which the bits have been deleted is subjected to channel decoding (turbo decoding) by decoder 30 and received data is thereby obtained.
FIG. 2 is a block diagram showing the internal configuration of coder 11 of OFDM transmission apparatus 10. In this figure, systematic bit sequence (transmission data) u is output as systematic bit sequence X1 as is, while it is also input to element coder 31 and interleaver 32. Element coder 31 generates a codeword for input systematic bit sequence u. The generated codeword is output as parity bit sequence X2.
Interleaver 32 has a conversion function for converting a read order corresponding to a write order and outputs input systematic bit sequence u to element coder 33 in a different order from the input order. Element coder 33 generates a codeword for the bit sequence output from interleaver 32. The generated codeword is output as parity bit sequence X3.
FIG. 3 is a block diagram showing the internal configuration of decoder 30 of OFDM reception apparatus 20. The received signal sequences have noise (assumed to be additive white Gaussian noise here) and correspond to a systematic bit and a parity bit respectively. These received signal sequences are input to decoder 30.
Element decoder 41 performs decoding processing on the received signal sequence corresponding to systematic bit sequence X1 (hereinafter referred to as “systematic part Y1”) and the received signal sequence corresponding to parity bit sequence X2 (hereinafter referred to as “parity part Y2”) together with a priori value La1 which is reliability information transmitted from deinterleaver 45 and outputs external value Le1 to interleaver 42. The external value indicates the increase in symbol reliability by the element decoder. External value Le1 is rearranged by interleaver 42 and input to element decoder 44 as a priori value La2. Note that decoding by element decoder 44 is not performed in a first iteration, and therefore 0 is assigned as a priority value.
Element decoder 44 receives a sequence obtained by rearranging systematic part Y1 by interleaver 43, the received signal sequence corresponding to parity bit sequence X3 (hereinafter referred to as “parity part Y3”) and a priori value La2, performs decoding processing on them and outputs external value Le2 to deinterleaver 45. External value Le2 is subjected to an operation by deinterleaver 45 of restoring the order before rearranged by the interleaver, input to element decoder 41 as a priority value La1 and decoded repeatedly. After being decoded several or over ten times repeatedly, element decoder 44 calculates a posteriori value L2 defined as a logarithmic posterior probability ratio and deinterleaver 46 deinterleaves the calculation result. Hard decision section 47 then performs hard decision on the deinterleaved sequence, outputs the decoded bit sequence, and error detection section 48 performs error detection on the decoded bit sequence and outputs the detection result.
Non-Patent Document 1: C. Berrou, A. Glavieux “Near Optimum Error Correcting Coding And Decoding: Turbo-Codes,” IEEE Trans. Commun., Vol. 44, pp. 1261-1271, October 1996.